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ATmega128
Table 52. W aveform Generation Mode Bit Description
WGM01 (1)
WGM00 (1)
Timer/Counter
Update of
TOV0 Flag
Mode
0
1
(CTC0)
0
0
(PWM0)
0
1
Mode of Operation
Normal
P W M, Phase
TOP
0xFF
0xFF
OCR0 at
Immediate
TOP
Set on
MAX
BOTTOM
Correct
2
3
1
1
0
1
CTC
Fast P W M
OCR0
0xFF
Immediate
BOTTOM
MAX
MAX
Note:
1. The CTC0 and P W M0 bit definition names are now obsolete. Use the W GM01:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
? Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
W hen OC0 is connected to the pin, the function of the COM01:0 bits depends on the W GM01:0
bit setting. Table 53 shows the COM01:0 bit functionality when the W GM01:0 bits are set to a
normal or CTC mode (non-P W M).
Table 53. Compare Output Mode, non-P W M Mode
COM01
0
0
1
1
COM00
0
1
0
1
Description
Normal port operation, OC0 disconnected.
Toggle OC0 on compare match
Clear OC0 on compare match
Set OC0 on compare match
Table 54 shows the COM01:0 bit functionality when the W GM01:0 bits are set to fast P W M
mode.
Table 54. Compare Output Mode, Fast P W M Mode (1)
COM01
0
0
1
1
COM00
0
1
0
1
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match, set OC0 at BOTTOM,
(non-inverting mode)
Set OC0 on compare match, clear OC0 at BOTTOM,
(inverting mode)
Note:
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
match is ignored, but the set or clear is done at BOTTOM. See “Fast P W M Mode” on page 98
for more details.
Table 55 shows the COM01:0 bit functionality when the W GM01:0 bits are set to phase correct
P W M mode.
104
2467X–AVR–06/11
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